Instruction Reference

The 6502 has a relatively basic set of instructions, many having similar functions (e.g. memory access, arithmetic, etc.). The following sections list the complete set of 56 instructions in functional groups.

ADC AND ASL BCC BCS BEQ BIT BMI BNE BPL BRK BVC BVS CLC
CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY JMP
JSR LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI
RTS SBC SEC SED SEI STA STX STY TAX TAY TSX TXA TXS TYA

Addressing Modes

The 6502 processor provides several ways in which memory locations can be addressed. Some instructions support several different modes while others may only support one. In addition the two index registers can not always be used interchangeably. This lack of orthogonality in the instruction set is one of the features that makes the 6502 trickier to program well.
Implicit" Accumulator" Immediate"
Zero page" Zero page X" Zero page Y"
Relative" Absolute" Absolute X"
Absolute Y" Indirect" Indexed indirect"
Indirect indexed"
Load/Store Operations

These instructions transfer a single byte between memory and one of the registers. Load operations set the negative (N) and zero (Z) flags depending on the value of transferred. Store operations do not affect the flag settings.

LDA Load Accumulator

A,Z,N = M

A ⇐ M

Loads a byte of memory into the accumulator setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Immediate 0xA9 2 2
Zero Page 0xA5 2 3
Zero Page,X 0xB5 2 4
Absolute 0xAD 3 4
Absolute,X 0xBD 3 4 (+1 if page crossed)
Absolute,Y 0xB9 3 4 (+1 if page crossed)
(Indirect,X) 0xA1 2 6
(Indirect),Y 0xB1 2 5 (+1 if page crossed)
  • C Not affected
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of A is set
LDX Load X Register

X,Z,N = M

X ⇐ M

Loads a byte of memory into the X register setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Immediate 0xA2 2 2
Zero Page 0xA6 2 3
Zero Page,Y 0xB6 2 4
Absolute 0xAE 3 4
Absolute,Y 0xBE 3 4 (+1 if page crossed)
  • C Not affected
  • Z Set if X = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of X is set
LDY Load Y Register

Y,Z,N = M

Y ⇐ M

Loads a byte of memory into the Y register setting the zero and negative flags as appropriate.
Mode Opcode Bytes Cycles
Immediate 0xA0 2 2
Zero Page 0xA4 2 3
Zero Page,X 0xB4 2 4
Absolute 0xAC 3 4
Absolute,X 0xBC 3 4 (+1 if page crossed)
  • C Not affected
  • Z Set if Y = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of Y is set
STA Store Accumulator

M ⇐ A

Stores the contents of the accumulator into memory.
Mode Opcode Bytes Cycles
Zero Page 0x85 2 3
Zero Page,X 0x95 2 4
Absolute 0x8D 3 4
Absolute,X 0x9D 3 5
Absolute,Y 0x99 3 5
(Indirect,X) 0x81 2 6
(Indirect),Y 0x91 2 6
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
STX Store X Register

M ⇐ X

Stores the contents of the X register into memory.
Mode Opcode Bytes Cycles
Zero Page 0x86 2 3
Zero Page,Y 0x96 2 4
Absolute 0x8E 3 4
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
STY Store Y Register

M ⇐ Y

Stores the contents of the Y register into memory.
Mode Opcode Bytes Cycles
Zero Page 0x84 2 3
Zero Page,X 0x94 2 4
Absolute 0x8C 3 4
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
Register Transfers

The contents of the X and Y registers can be moved to or from the accumulator, setting the negative (N) and zero (Z) flags as appropriate.

TAX Transfer accumulator to X

X ⇐ A

Copies the current contents of the accumulator into the X register and sets the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0xAA 1 2
  • C Not affected
  • Z Set if X = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of X is set
TAY Transfer accumulator to Y

Y ⇐ A

Copies the current contents of the accumulator into the Y register and sets the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0xA8 1 2
  • C Not affected
  • Z Set if Y = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of Y is set
TXA Transfer X to accumulator

A ⇐ X

Copies the current contents of the X register into the accumulator and sets the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0x8A 1 2
  • C Not affected
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of A is set
TYA Transfer Y to accumulator

A ⇐ Y

Copies the current contents of the Y register into the accumulator and sets the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0x98 1 2
  • C Not affected
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of A is set
Stack Operations

The 6502 microprocessor supports a 256 byte stack fixed between memory locations 0x0100 and 0x01FF. A special 8-bit register, S, is used to keep track of the next free byte of stack space. Pushing a byte on to the stack causes the value to be stored at the current free location (e.g. 0x0100,S) and then the stack pointer is post decremented. Pull operations reverse this procedure.

The stack register can only be accessed by transferring its value to or from the X register. Its value is automatically modified by push/pull instructions, subroutine calls and returns, interrupts and returns from interrupts.

TSX Transfer stack pointer to X

X ⇐ S

Copies the current contents of the stack register into the X register and sets the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0xBA 1 2
  • C Not affected
  • Z Set if X = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of X is set
TXS Transfer X to stack pointer

S ⇐ X

Copies the current contents of the X register into the stack register.

Mode Opcode Bytes Cycles
Implied 0x9A 1 2
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
PHA Push accumulator on stack

Pushes a copy of the accumulator on to the stack.
Mode Opcode Bytes Cycles
Implied 0x48 1 3
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
PHP Push processor status on stack

Pushes a copy of the status flags on to the stack.
Mode Opcode Bytes Cycles
Implied 0x08 1 3
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
PLA Pull accumulator from stack

Pulls an 8 bit value from the stack and into the accumulator. The zero and negative flags are set as appropriate.

Mode Opcode Bytes Cycles
Implied 0x68 1 4
  • C Not affected
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of A is set
PLP Pull processor status from stack

Pulls an 8 bit value from the stack and into the processor flags. The flags will take on new states as determined by the value pulled.

Mode Opcode Bytes Cycles
Implied 0x28 1 4
  • C Set from stack
  • Z Set from stack
  • I Set from stack
  • D Set from stack
  • B Set from stack
  • V Set from stack
  • N Set from stack
Logical

The following instructions perform logical operations on the contents of the accumulator and another value held in memory. The BIT instruction performs a logical AND to test the presence of bits in the memory value to set the flags but does not keep the result.

AND Logical AND

A,Z,N = A&M

A logical AND is performed, bit by bit, on the accumulator contents using the contents of a byte of memory.

Mode Opcode Bytes Cycles
Immediate 0x29 2 2
Zero Page 0x25 2 3
Zero Page,X 0x35 2 4
Absolute 0x2D 3 4
Absolute,X 0x3D 3 4 (+1 if page crossed)
Absolute,Y 0x39 3 4 (+1 if page crossed)
(Indirect,X) 0x21 2 6
(Indirect),Y 0x31 2 5 (+1 if page crossed)
  • C Not affected
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 set
EOR Exclusive OR

A,Z,N = A^M

An exclusive OR is performed, bit by bit, on the accumulator contents using the contents of a byte of memory.

Mode Opcode Bytes Cycles
Immediate 0x49 2 2
Zero Page 0x45 2 3
Zero Page,X 0x55 2 4
Absolute 0x4D 3 4
Absolute,X 0x5D 3 4 (+1 if page crossed)
Absolute,Y 0x59 3 4 (+1 if page crossed)
(Indirect,X) 0x41 2 6
(Indirect),Y 0x51 2 5 (+1 if page crossed)
  • C Not affected
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 set
ORA Logical Inclusive OR

A,Z,N = A|M

An inclusive OR is performed, bit by bit, on the accumulator contents using the contents of a byte of memory.

Mode Opcode Bytes Cycles
Immediate 0x09 2 2
Zero Page 0x05 2 3
Zero Page,X 0x15 2 4
Absolute 0x0D

3

 4
Absolute,X 0x1D 3 4 (+1 if page crossed)
Absolute,Y 0x19 3 4 (+1 if page crossed)
(Indirect,X) 0x01 2 6
(Indirect),Y 0x11 2 5 (+1 if page crossed)
  • C Not affected
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 set
BIT Bit Test

A & M, N = M7, V = M6

This instructions is used to test if one or more bits are set in a target memory location. The mask pattern in A is ANDed with the value in memory to set or clear the zero flag, but the result is not kept. Bits 7 and 6 of the value from memory are copied into the N and V flags.

Mode Opcode Bytes Cycles
Zero Page 0x24 2 3
Absolute 0x2C 3 4
  • C Not affected
  • Z Set if the result if the AND is zero
  • I Not affected
  • D Not affected
  • B Not affected
  • V Set to bit 6 of the memory value
  • N Set to bit 7 of the memory value
Arithmetic

The arithmetic operations perform addition and subtraction on the contents of the accumulator. The compare operations allow the comparison of the accumulator and X or Y with memory values.

ADC Add with Carry

A,Z,C,N = A+M+C

This instruction adds the contents of a memory location to the accumulator together with the carry bit. If overflow occurs the carry bit is set, this enables multiple byte addition to be performed.

Mode Opcode Bytes Cycles
Immediate 0x69 2 2
Zero Page 0x65 2 3
Zero Page,X 0x75 2 4
Absolute 0x6D 3 4
Absolute,X 0x7D 3 4 (+1 if page crossed)
Absolute,Y 0x79 3 4 (+1 if page crossed)
(Indirect,X) 0x61 2 6
(Indirect),Y 0x71 2 5 (+1 if page crossed)
  • C Set if overflow in bit 7
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Set if sign bit is incorrect
  • N Set if bit 7 set
SBC Subtract with Carry

A,Z,C,N = A-M-(1-C)

This instruction subtracts the contents of a memory location to the accumulator together with the not of the carry bit. If overflow occurs the carry bit is clear, this enables multiple byte subtraction to be performed.

Mode Opcode Bytes Cycles
Immediate 0xE9 2 2
Zero Page 0xE5 2 3
Zero Page,X 0xF5 2 4
Absolute 0xED 3 4
Absolute,X 0xFD 3 4 (+1 if page crossed)
Absolute,Y 0xF9 3 4 (+1 if page crossed)
(Indirect,X) 0xE1 2 6
(Indirect),Y 0xF1 2 5 (+1 if page crossed)
  • C Clear if overflow in bit 7
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Set if sign bit is incorrect
  • N Set if bit 7 set
CMP Compare accumulator

Z,C,N = A-M

This instruction compares the contents of the accumulator with another memory held value and sets the zero and carry flags as appropriate.

Mode Opcode Bytes Cycles
Immediate 0xC9 2 2
Zero Page 0xC5 2 3
Zero Page,X 0xD5 2 4
Absolute 0xCD 3 4
Absolute,X 0xDD 3 4 (+1 if page crossed)
Absolute,Y 0xD9 3 4 (+1 if page crossed)
(Indirect,X) 0xC1 2 6
(Indirect),Y 0xD1 2 5 (+1 if page crossed)
  • C Set if A >= M
  • Z Set if A = M
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
CPX Compare X register

Z,C,N = X-M

This instruction compares the contents of the X register with another memory held value and sets the zero and carry flags as appropriate.

Mode Opcode Bytes Cycles
Immediate 0xE0 2 2
Zero Page 0xE4 2 3
Absolute 0xEC 3 4
  • C Set if X >= M
  • Z Set if X = M
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
CPY Compare Y register

Z,C,N = Y-M

This instruction compares the contents of the Y register with another memory held value and sets the zero and carry flags as appropriate.

Mode Opcode Bytes Cycles
Immediate 0xC0 2 2
Zero Page 0xC4 2 3
Absolute 0xCC 3 4
  • C Set if Y >= M
  • Z Set if Y = M
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
Increments & Decrements

Increment or decrement a memory location or one of the X or Y registers by one setting the negative (N) and zero (Z) flags as appropriate,

INC Increment a memory location

M,Z,N = M+1

Adds one to the value held at a specified memory location setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Zero Page 0xE6 2 5
Zero Page,X 0xF6 2 6
Absolute 0xEE 3 6
Absolute,X 0xFE 3 7
  • C Not affected
  • Z Set if result is zero
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
INX Increment the X register

X,Z,N = X+1

Adds one to the X register setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0xE8 1 2
  • C Not affected
  • Z Set if X is zero
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of X is set
INY Increment the Y register

Y,Z,N = Y+1

Adds one to the Y register setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0xC8 1 2
  • C Not affected
  • Z Set if Y is zero
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of Y is set
DEC Decrement a memory location

M,Z,N = M-1

Subtracts one from the value held at a specified memory location setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Zero Page 0xC6 2 5
Zero Page,X 0xD6 2 6
Absolute 0xCE 3 6
Absolute,X 0xDE 3 7
  • C Not affected
  • Z Set if result is zero
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
DEX Decrement the X register

X,Z,N = X-1

Subtracts one from the X register setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0xCA 1 2
  • C Not affected
  • Z Set if X is zero
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of X is set
DEY Decrement the Y register

Y,Z,N = Y-1

Subtracts one from the Y register setting the zero and negative flags as appropriate.

Mode Opcode Bytes Cycles
Implied 0x88 1 2
  • C Not affected
  • Z Set if Y is zero
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of Y is set
Shifts

Shift instructions cause the bits within either a memory location or the accumulator to be shifted by one bit position. The rotate instructions use the contents if the carry flag (C) to fill the vacant position generated by the shift and to catch the overflowing bit. The arithmetic and logical shifts shift in an appropriate 0 or 1 bit as appropriate but catch the overflow bit in the carry flag (C).

ASL Arithmetic Shift Left

A,Z,C,N = M*2 or M,Z,C,N = M*2

This operation shifts all the bits of the accumulator or memory contents one bit left. Bit 0 is set to 0 and bit 7 is placed in the carry flag. The effect of this operation is to multiply the memory contents by 2 (ignoring 2's complement considerations), setting the carry if the result will not fit in 8 bits.

Mode Opcode Bytes Cycles
Accumulator 0x0A 1 2
Zero Page 0x06 2 5
Zero Page,X 0x16 2 6
Absolute 0x0E 3 6
Absolute,X 0x1E 3 7
  • C Set to contents of old bit 7
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
LSR Logical Shift Right

A,C,Z,N = A/2 or M,C,Z,N = M/2

Each of the bits in A or M is shift one place to the right. The bit that was in bit 0 is shifted into the carry flag. Bit 7 is set to zero.

Mode Opcode Bytes Cycles
Accumulator 0x4A 1 2
Zero Page 0x46 2 5
Zero Page,X 0x56 2 6
Absolute 0x4E 3 6
Absolute,X 0x5E 3 7
  • C Set to contents of old bit 0
  • Z Set if result = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
ROL Rotate Left

Move each of the bits in either A or M one place to the left. Bit 0 is filled with the current value of the carry flag whilst the old bit 7 becomes the new carry flag value.

Mode Opcode Bytes Cycles
Accumulator 0x2A 1 2
Zero Page 0x26 2 5
Zero Page,X 0x36 2 6
Absolute 0x2E 3 6
Absolute,X 0x3E 3 7
  • C Set to contents of old bit 7
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
ROR Rotate Right

Move each of the bits in either A or M one place to the right. Bit 7 is filled with the current value of the carry flag whilst the old bit 0 becomes the new carry flag value.

Mode Opcode Bytes Cycles
Accumulator 0x6A 1 2
Zero Page 0x66 2 5
Zero Page,X 0x76 2 6
Absolute 0x6E 3 6
Absolute,X 0x7E 3 7
  • C Set to contents of old bit 0
  • Z Set if A = 0
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Set if bit 7 of the result is set
Jumps & Calls

The following instructions modify the program counter causing a break to normal sequential execution. The JSR instruction pushes the old PC onto the stack before changing it to the new location allowing a subsequent RTS to return execution to the instruction after the call.

JMP Jump to another location

Sets the program counter to the address specified by the operand.
Mode Opcode Bytes Cycles
Absolute 0x4C 3 3
Indirect  0x6C 3 5
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
JSR Jump to a subroutine

The JSR instruction pushes the address (minus one) of the return point on to the stack and then sets the program counter to the target memory address.

Mode Opcode Bytes Cycles
Absolute 0x20 3 6
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
RTS Return from subroutine

The RTS instruction is used at the end of a subroutine to return to the calling routine. It pulls the program counter (minus one) from the stack.

Mode Opcode Bytes Cycles
Implied 0x60 1 6
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
Branches

Branch instructions break the normal sequential flow of execution by changing the program counter if a specified condition is met. All the conditions are based on examining a single bit within the processor status.

BCC Branch if carry flag clear

If the carry flag is clear then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0x90 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
BCS Branch if carry flag set

If the carry flag is set then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0xB0 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
BEQ Branch if zero flag set

If the zero flag is set then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0xF0 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
BMI Branch if negative flag set

If the negative flag is set then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0x30 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
BNE Branch if zero flag clear

If the zero flag is clear then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0xD0 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
BPL Branch if negative flag clear

If the negative flag is clear then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0x10 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
BVC Branch if overflow flag clear

If the overflow flag is clear then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0x50 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
BVS Branch if overflow flag set

If the overflow flag is set then add the relative displacement to the program counter to cause a branch to a new location.

Mode Opcode Bytes Cycles
Relative 0x70 2 2 (+1 if branch succeeds
+2 if to a new page)
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
Status Flag Changes

The following instructions change the values of specific status flags.

CLC Clear carry flag

C = 0

 C
Mode Opcode Bytes Cycles
Implied 0x18 1 2
  • C Set to 0
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
CLD Clear decimal mode flag

D = 0

 D
Mode Opcode Bytes Cycles
Implied 0xD8 1 2
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Set to 0
  • B Not affected
  • V Not affected
  • N Not affected
CLI Clear interrupt disable flag

I = 0

Clears the interrupt disable flag allowing normal interrupt requests to be serviced.

Mode Opcode Bytes Cycles
Implied 0x58 1 2
  • C Not affected
  • Z Not affected
  • I Set to 0
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
CLV Clear overflow flag

V = 0

Clears the overflow flag.
Mode Opcode Bytes Cycles
Implied 0xB8 1 2
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Set to 0
  • N Not affected
SEC Set carry flag

C = 1

Set the carry flag to one.
Mode Opcode Bytes Cycles
Implied 0x38 1 2
  • C Set to 1
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
SED Set decimal mode flag

D = 1

Set the decimal mode flag to one.
Mode Opcode Bytes Cycles
Implied 0xF8 1 2
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Set to 1
  • B Not affected
  • V Not affected
  • N Not affected
SEI Set interrupt disable flag

I = 1

Set the interrupt disable flag to one.
Mode Opcode Bytes Cycles
Implied 0x78 1 2
  • C Not affected
  • Z Not affected
  • I Set to 1
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
System Functions

The remaining instructions perform useful but rarely used functions.
BRK Force an interrupt

The BRK instruction forces the generation of an interrupt request. The program counter and processor status are pushed on the stack then the IRQ interrupt vector at 0xFFFE/F is loaded into the PC and the break flag in the status set to one.

Mode Opcode Bytes Cycles
Implied 0x00 1 7
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Set to 1
  • V Not affected
  • N Not affected
NOP No Operation

The NOP instruction causes no changes to the processor other than the normal incrementing of the program counter to the next instruction.

Mode Opcode Bytes Cycles
Implied 0xEA 1 2
  • C Not affected
  • Z Not affected
  • I Not affected
  • D Not affected
  • B Not affected
  • V Not affected
  • N Not affected
RTI Return from Interrupt

The RTI instruction is used at the end of an interrupt processing routine. It pulls the processor flags from the stack followed by the program counter.

Mode Opcode Bytes Cycles
Implied 0x40 1 6
  • C Set from stack
  • Z Set from stack
  • I Set from stack
  • D Set from stack
  • B Set from stack
  • V Set from stack
  • N Set from stack

Addressing Modes

The 6502 processor provides several ways in which memory locations can be addressed. Some instructions support several different modes while others may only support one. In addition the two index registers can not always be used interchangeably. This lack of orthogonality in the instruction set is one of the features that makes the 6502 trickier to program well.

Implicit

For many 6502 instructions the source and destination of the information to be manipulated is implied directly by the function of the instruction itself and no further operand needs to be specified. Operations like 'Clear Carry Flag' (#CLC) and 'Return from Subroutine' (#RTS) are implicit.

Accumulator

Some instructions have an option to operate directly upon the accumulator. The programmer specifies this by using a special operand value, 'A'. For example:

LSR A           ;Logical shift right one bit
ROR A           ;Rotate right one bit

Immediate

Immediate addressing allows the programmer to directly specify an 8 bit constant within the instruction. It is indicated by a '#' symbol followed by an numeric expression. For example:

LDA #10         ;Load 10 ($0A) into the accumulator
LDX #LO LABEL   ;Load the LSB of a 16 bit address into X
LDY #HI LABEL   ;Load the MSB of a 16 bit address into Y

Zero Page

An instruction using zero page addressing mode has only an 8 bit address operand. This limits it to addressing only the first 256 bytes of memory (e.g. $0000 to $00FF) where the most significant byte of the address is always zero. In zero page mode only the least significant byte of the address is held in the instruction making it shorter by one byte (important for space saving) and one less memory fetch during execution (important for speed).

An assembler will automatically select zero page addressing mode if the operand evaluates to a zero page address and the instruction supports the mode (not all do).

LDA $00         ;Load accumulator from $00
ASL ANSWER      ;Shift labelled location ANSWER left

Zero Page,X

The address to be accessed by an instruction using indexed zero page addressing is calculated by taking the 8 bit zero page address from the instruction and adding the current value of the X register to it. For example if the X register contains $0F and the instruction LDA $80,X is executed then the accumulator will be loaded from $008F (e.g. $80 + $0F => $8F).

NB: The address calculation wraps around if the sum of the base address and the register exceed $FF. If we repeat the last example but with $FF in the X register then the accumulator will be loaded from $007F (e.g. $80 + $FF => $7F) and not $017F.

STY $10,X       ;Save the Y register at location on zero page
AND TEMP,X      ;Logical AND accumulator with a zero page value

Zero Page,Y

The address to be accessed by an instruction using indexed zero page addressing is calculated by taking the 8 bit zero page address from the instruction and adding the current value of the Y register to it. This mode can only be used with the #LDX and #STX instructions.

LDX $10,Y       ;Load the X register from a location on zero page
STX TEMP,Y      ;Store the X register in a location on zero page

Relative

Relative addressing mode is used by branch instructions (e.g. #BEQ, #BNE, etc.) which contain a signed 8 bit relative offset (e.g. -128 to +127) which is added to program counter if the condition is true. As the program counter itself is incremented during instruction execution by two the effective address range for the target instruction must be with -126 to +129 bytes of the branch.

BEQ LABEL       ;Branch if zero flag set to LABEL
BNE *+4         ;Skip over the following 2 byte instruction

Absolute

Instructions using absolute addressing contain a full 16 bit address to identify the target location.

JMP $1234       ;Jump to location $1234
JSR WIBBLE      ;Call subroutine WIBBLE

Absolute,X

The address to be accessed by an instruction using X register indexed absolute addressing is computed by taking the 16 bit address from the instruction and added the contents of the X register. For example if X contains $92 then an STA $2000,X instruction will store the accumulator at $2092 (e.g. $2000 + $92).

STA $3000,X     ;Store accumulator between $3000 and $30FF
ROR CRC,X       ;Rotate right one bit

Absolute,Y

The Y register indexed absolute addressing mode is the same as the previous mode only with the contents of the Y register added to the 16 bit address from the instruction.

AND $4000,Y     ;Perform a logical AND with a byte of memory
STA MEM,Y       ;Store accumulator in memory

Indirect

#JMP is the only 6502 instruction to support indirection. The instruction contains a 16 bit address which identifies the location of the least significant byte of another 16 bit memory address which is the real target of the instruction.

For example if location $0120 contains $FC and location $0121 contains $BA then the instruction JMP ($0120) will cause the next instruction execution to occur at $BAFC (e.g. the contents of $0120 and $0121).

JMP ($FFFC)     ;Force a power on reset
JMP (TARGET)    ;Jump via a labelled memory area

Indexed Indirect

Indexed indirect addressing is normally used in conjunction with a table of address held on zero page. The address of the table is taken from the instruction and the X register added to it (with zero page wrap around) to give the location of the least significant byte of the target address.

LDA ($40,X)     ;Load a byte indirectly from memory
STA (MEM,X)     ;Store accumulator indirectly into memory

Indirect Indexed

Indirect indirect addressing is the most common indirection mode used on the 6502. In instruction contains the zero page location of the least significant byte of 16 bit address. The Y register is dynamically added to this value to generated the actual target address for operation.

LDA ($40),Y     ;Load a byte indirectly from memory
STA (DST),Y     ;Store accumulator indirectly into memory

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